In Dual Data Rate (DDR) memory systems, a memory controller queues auto-refreshes (ARs) to a memory device. During normal operation mode, the controller schedules refreshes in bursts to maximize performance. The memory device may include logic and/or features to maintain an internal refresh counter that tracks bank rows of an array of memory cells that get refreshed. When each AR command is received, the memory device may either increment or decrement the refresh counter.
With increased DRAM densities, the number of total pages to be refreshed increases substantially and, as a result, the overall refresh operation consumes an increasing amount of power. Because the controller must refresh all memory locations, whether or not the location is used for data, much power is wasted on unnecessary refreshes.